The present invention relates to frame buffer memory systems for raster displays, and more particularly to a bus architecture and communications method for interfacing a picture processor to a frame buffer.
Raster scan, frame buffer displays have become increasingly popular as the price of semiconductor memory has decreased. The image to be displayed is represented in a large memory that saves a digital representation of the intensity and/or color of each picture element, or pixel, on the screen. The frame buffer memory is equipped with hardware to generate a video signal to refresh the display and with a memory port to allow a host computer or display processor to change the frame buffer memory in order to change the image being displayed. A general overview of the art can be found in Raster Graphics Handbook, published by Conrac Division, Conrac Corporation, Covina, Calif. 91722 (1980).
Interactive graphics applications require rapid changes to the displayed image, which in turn require rapid changes to the frame buffer memory. Although the speed of the host processor and display processor is clearly important to high performance, so also are the properties of the memory system, such as update bandwidth, i.e., the rate at which the host processor or data processor may access each pixel. Many graphics systems are partitioned such that the image rendering engine is separated from the frame buffer by some kind of bus. In a low end system, where the rendering engine is a generic microprocessor and the frame buffer is a dualported memory, this bus may be the system bus. In a high-end system, such as an engineering workstation, where the rendering engine is a special purpose picture processor, this bus may be a high-speed private bus between the picture processor and the frame buffer. In either case, for drawing vectors of arbitrary orientation, it is necessary to send the address and data across the bus for every pixel to be written. This means that there must either be enough bus signal lines to send both the address and the data at the same time or, if it is a multiplexed address/data bus, every pixel write must be an address cycle followed by a data cycle.
In conventional raster display systems, a two-dimensional block of data (three-dimensional in color systems) is created in the frame buffer to represent an image to be displayed. Each data element defines a pixel, the pixel data consisting of an address defining the two-dimensional coordinates of the pixel, and a value, represented by a single binary bit in monochrome systems, and a number of bits in color systems. The pixel data is generated and transmitted a pixel at a time, first the address, then the pixel value, to the frame buffer control circuitry. This circuitry reads the address and places the corresponding pixel value into the frame buffer. This process is repeated for all of the pixels to be changed in the image. Having to send the address each time a pixel value is sent consumes much of the bandwidth of the communications interface between the display processor and the frame buffer.
Most bus systems have a "block transfer" mode to increase the data transfer bandwidth. In this mode, one address can be followed by multiple data words which are written to sequential memory locations beginning at the initial address. This mode can be used for sending vectors aligned with the X-axis or Y-axis but is not generally useful, however, for drawing vectors of arbitrary orientation into a frame buffer. This is because frame buffers are logically organized as a x-y array and the physical memory address is a combination of the x and y addresses. Since vectors of arbitrary orientation can go in any direction, the adjacent pixel addresses are not, in general, sequential memory addresses.
U.S. Pat. No. 4,586,037 to Rosener et al., incorporated herein, discloses octant register circuitry and a mode of operation that enable a full address to be sent along with a pixel value for such address to the frame buffer memory to define the starting point of a vector. Successive pixel data is sent in parallel with a three-bit address defining the octant in which the next pixel value will be placed relative to the previous address. The three-bit octant data thus defines the location of a next pixel to be written adjacent an immediately preceding pixel, without having to send the entire address before each pixel. Using this approach, particularly in application of line drawing algorithms in large memory arrays, can greatly improve efficiency but still requires at least three bits besides the data.
Another area of interest has to do with the drawing of images, such as cursors and lines, over images already being displayed, and movement of the line or cursor images without destroying the underlying image stored in the frame buffer. U.S. Pat. No. 4,197,590 to Sukonick et al. discloses an exclusive or (XOR) which allows a selective erase that restores lines crossing or concurrent with erased lines. XOR feature permits part of the drawing to be moved or dragged into place without erasing other parts of the drawing. This approach requires substantial computational overhead and has a number of operational limitations. Another approach, developed by Xerox Palo Alto Research Center and described by D. H. H. Engles, "The Small Talk Graphics Kernel" BYTE, August, 1981, pp. 168-194, incorporated herein, is an operation called "Bit Blt." The Bit Blt process uses a rectangular bit map to define the image to be written into the frame buffer. As the image is written into the frame buffer, the prior information in the same address locations is read out and stored in a separate memory. When the new image is moved or deleted, the old information is restored to the frame buffer in its original location. This method is suitably efficient when applied to nearly rectangular blocks of pixel data, particularly those of small size as in the case of a cursor image. Its efficiency is greatly reduced, however, when large portions of the pre-existing image must be stored and restored. That is the case even when relatively simple new images are to be placed on the display, such as lines, curves, or simple polygons.
Another communications interface limitation in prior raster display systems relates to the way information is relayed, or pipelined, through multiple data processing stages. U.S. Pat. No. 4,658,247 to Gharachorloo discloses an example of a prior graphics display system which uses a line buffer pipeline connecting a series of pixel processors to implement real-time image generation. In an ideal pipeline through the system, all stages process their respective data in the same amount of time. The data transfer mechanism between stages can be a simple register which is loaded with new data at the end of each processing cycle by a pipeline clock that is common to all pipeline stages. Problems arise, however, when one of the pipe-stages takes longer than one pipeline clock cycle to process its data. If that happens, that stage must be able to halt the data flowing to it from the previous stage while it finishes its processing, or break up its process into more than one pipe stage. The problem worsens if the time it takes for a pipe stage to complete its process is variable, depending either on its input data or on some random or pseudo-random event happening within the pipe stage. If that is the case, the only thing that can be done is to somehow stop the previous or upstream process from sending new data until a slower, downstream process is ready to accept it. This means that each process must have knowledge of the state of all of the following pipe stages, that is, whether or not they are ready to receive new data. The simplest way to implement this is to send a hold signal from a current stage to a previous pipe stage. This hold signal is a busy signal from the current stage logically ORed with the hold signal coming from a following or downstream stage. Because of the signal delay associated with each OR gate, however, this scheme is not appropriate for a high-speed system with many stages, especially if the implementation is a bus structured system.
Accordingly, a need remains for improvements in the architecture and communications protocols employed in a raster scan display system for generating and transmitting pixel data to and from the frame buffer.